IS/SOC Design
System Design
- Architecture Development
- Spec Development & Micro Architecture
- IP/VIP Development
- Bus Protocols - AXI, AHB, ASB, APB, AMBA, CoreConnect
- CPU – ARM, RISC-V & IA
- High Speed Serial – PCIe 3/4/5, USB3/4, UFS, OPI, 5G Ethernet
- Legacy Serial Interfaces – I2C, SPI, CAN, UART
- Memory Controllers – DDR 3/4/5, SD Card
IS/SOC Design
CUSTOM CIRCUIT DESIGN
- Analog/Mix Mode Design & Verification
- High Performance PHYs – SERDES, PCIe3/4, USB3.1, 10GKR
- Amplifiers - multi-stage, Telescopic, Folded-Cascade
- Custom IPs – IOs, VCO, Charge Pump, CTLE, ADC/DAC, Serializer, Buffers (Analog, CML-based), ATB, Voltage Regulators & DC-DC Converters
- RF, Flash Design & Integration
- Standard Cell & Library Development
IS/SOC Design
LOGIC DESIGN & VERIFICATION
- Behavioral Modeling
- Spec-to-RTL
- RTL Design & Verification – supports IPs listed above
- IP & SOC Functional Verification (OVM/UVM)
- Verification IP Development
- Simulation & Code Coverage
IS/SOC Design
STRUCTURAL DESIGN
- Logic Partitioning
- Die Planning
- IP / VIP Development
- RTL Synthesis
- Timing & Static Timing Analysis
- DFT (JTAG,BIST) & ATPG
- Tools: ICC2, Fusion Compiler, PrimeTime PX, Power Pro, Power Artist, Formality, Design Compiler, CoreConsultant
IS/SOC Design
PHYSICAL DESIGN
- Floor Planning
- Placement & Routing
- Power Planning
- Clock Tree Synthesis
- Physical Verification (DRC/LVS)
- 5nm, 7nm, 10nm, 12nm,14nm, 16nm FinFET Process
- 22nm -130nm HVCMOS Process
IS/SOC Design
POST-SILICON SERVICES
- Silicon Validation
- Hardware Emulation
- FPGA proto-typing
- Co-Simulation Setup and Validation
- Test/Validation Board Devp
- Chip Bring Up & Silicon Turn-on
IS/SOC Design
CUSTOM CIRCUIT DESIGN
- Architecture Development
- Spec Development & Micro Architecture
- IP/VIP Development
- Bus Protocols - AXI, AHB, ASB, APB, AMBA, CoreConnect
- CPU – ARM, RISC-V & IA
- High Speed Serial – PCIe 3/4/5, USB3/4, UFS, OPI, 5G Ethernet
- Legacy Serial Interfaces – I2C, SPI, CAN, UART
- Memory Controllers – DDR 3/4/5, SD Card
CUSTOM CIRCUIT DESIGN
- Analog/Mix Mode Design & Verification
- High Performance PHYs – SERDES, PCIe3/4, USB3.1, 10GKR
- Amplifiers - multi-stage, Telescopic, Folded-Cascade
- Custom IPs – IOs, VCO, Charge Pump, CTLE, ADC/DAC, Serializer, Buffers (Analog, CML-based), ATB, Voltage Regulators & DC-DC Converters
- RF, Flash Design & Integration
- Standard Cell & Library Development
IS/SOC Design
LOGIC DESIGN & VERIFICATION
- Behavioral Modeling
- Spec-to-RTL
- RTL Design & Verification – supports IPs listed above
- IP & SOC Functional Verification (OVM/UVM)
- Verification IP Development
- Simulation & Code Coverage
IS/SOC Design
STRUCTURAL DESIGN
- Logic Partitioning
- Die Planning
- IP / VIP Development
- RTL Synthesis
- Timing & Static Timing Analysis
- DFT (JTAG,BIST) & ATPG
- Tools: ICC2, Fusion Compiler, PrimeTime PX, Power Pro, Power Artist, Formality, Design Compiler, CoreConsultant
IS/SOC Design
PHYSICAL DESIGN
- Floor Planning
- Placement & Routing
- Power Planning
- Clock Tree Synthesis
- Physical Verification (DRC/LVS)
- 5nm, 7nm, 10nm, 12nm,14nm, 16nm FinFET Process
- 22nm -130nm HVCMOS Process
IS/SOC Design
POST-SILICON SERVICES
- Silicon Validation
- Hardware Emulation
- FPGA proto-typing
- Co-Simulation Setup and Validation
- Test/Validation Board Devp
- Chip Bring Up & Silicon Turn-on